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A secure and dynamic multi keyword ranked

A distributed three hop routing protocol to

Vlsi assisted nonrigid registration using modified demons algorithm

Two step optimization approach for the design of multiplierless linear-phase fir filters

Timing error tolerance in small core designs for so c applications

Synthesis of genetic clock with combinational biologic circuits

Signal design for multiple antenna systems with spatial multiplexing and noncoherent reception

Shift register design using two bit flip flop

Reverse converter design via parallel prefix adders novel components, methodology, and implementations

Recursive approach to the design of a parallel self timed adder

Range unlimited delay interleaving and –recycling clock skew compensation and duty-cycle correction circuit

Pre encoded multipliers based on non-redundant radix-4 signed-digit encoding

Partially parallel encoder architecture for long polar codes

Obfuscating dsp circuits via high level transformations

Novel design algorithm for low complexity programmable fir filters based on extended double base number system

Modulation classification of single input multiple-output signals using asynchronous sensors

Minimum parallel binary adders with nor (nand) gates

Low cost high-performance vlsi architecture for montgomery modular multiplication

Learning weighted lower linear envelope potentials in binary markov random fields

Integrating lock free and combining techniques for a practical and scalable fifo queue